Lab 8 – Flip Flops

No, this isn’t a political commentary, but a post on my most recent lab for my Digital Circuit Logic class.

Today’s lab was about Flip-Flops, a nifty little toy that “remembers” previous inputs and uses them to determine future inputs.  I still am having trouble with the how and why, but when it comes to labs, this one was refreshingly easy.

Part 1: manually build an S-R latch:

Cake.  As seen below, just feed the output of one NOR gate into the other and use a S (set) and R (reset) as the inputs.  Your outputs are Q and Q’.

Part 2: Manually build a D Flip-Flop

This, in and of itself is not difficult. Start with a S-R latch and connect S and R each to the output of their own AND gate. Then the AND gates are connected to a clock and a “data” (D) and repeated. I had trouble implementing this circuit only because of human error. I was using NAND gates rather than NOR gates with my S-R latch, which in this case always returned TRUE. Check the figure below.

Part 3: Construct a T latch with a J-K latch:

This was cake. Straight from the book. Just connect J and K together and call it T and hook up the clock so that it will “toggle” the output if J=1 and do nothing if J=0. Again, diagrams:

That was this week’s lab. It was really nice to be able to get it done in only an hour or so, rather than 4.



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